The present invention relates to timing analysis in digital integrated circuit design, and more specifically, to parallel multi-threaded common path pessimism removal in multiple paths.
Timing analysis is an important aspect of digital integrated circuit (IC) or chip design and is performed at various stages to ensure that the end product will meet all timing requirements. A chip design is modeled as a timing graph with gate- and wire-pins denoted by timing nodes. Each connection from an input pin (source node) to an output pin (sink node) is denoted by a directed timing edge in the graph. Generally, timing analysis involves calculating delay through the edges or paths between a chip input and a chip output to determine the speed of propagation of the arrival time of a signal at different components (e.g., gates, wires, latches) of the chip. Generally, arrival time at a given point refers to the time at which the voltage at the point reaches half of the maximum voltage. To account for on-chip and environmental variations (e.g., temperature, battery level), statistical static timing analysis (SSTA) may be used to express arrival time as a range given by {early mode arrival time, late mode arrival time}. A variety of tests may be implemented as part of the timing analysis. For example, a setup test compares the late mode arrival time at a data input node with the early mode arrival time at an external clock input node of the same device. If the late mode arrival time of the data is earlier than the early mode arrival time of the clock signal, then the test is passed because the data can be correctly captured. The issue of pessimism arises in timing analysis tests when early mode and late mode is considered for the same edge (path). For example, in the setup test example, if the data input and clock input shared an edge (a path segment), the test uses late mode arrival time with respect to the data input, which considers late mode delay through that edge, as well as early mode arrival time with respect to the clock input, which considers early mode delay through that same edge. This is referred to as common path pessimism (CPP).